当前位置:
首页 资源下载
搜索资源 - floating point addition verilog
搜索资源列表
-
1下载:
verilog编写的32位浮点加法器-32-bit Floating Point Addition Written in Verilog
-
-
0下载:
CAN总线的FPGA实现,用Verilog编写,代码完整,而且有很完善的测试代码,用ISE直接打开,学习FPGA进阶的好项目-CAN Bus FPGA, written with Verilog, code integrity, but also very good test code, using ISE directly open, a good project to learn advanced FPGA
-
-
2下载:
verilog写的浮点运算加法,希望对大家有用处-verilog to write floating point addition, we want to be useful
-
-
0下载:
Simple floating point addition unit written in Verilog
-
-
1下载:
浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算,结合vhdl和EPGA可编程技术,完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmab
-
-
0下载:
该源码利用Verilog HDL语言成功实现了浮点数的加法运算,包括全部工程以及Verilog 源码,经验证,该程序成功实现了浮点数的加法。-The use of Verilog HDL source language of the successful implementation of floating-point addition operation, including all engineering and Verilog source code, proven, successful
-
-
1下载:
使用verilog写的32位浮点数加法模块、浮点数乘法模块、浮点数除法模块、浮点数指数模块。指数模块是综合前面三个例化成泰勒级数求指数,迭代次数(可设置)决定了精度。-Use verilog write 32-bit floating-point addition module, floating-point multiplication module, floating-point division module, the floating point number index module.
-
-
0下载:
32位浮点数加法,使用的语言是verilog。其中包括的是工程中的v文件。-32-bit floating-point addition, the use of language is verilog. Including is v of the engineering documents.
-
-
1下载:
能够实现单精度浮点加法运算。输入引脚有:第一运算数,第二运算数,复位信号,时钟信号。输出信号有:运算结果,运算完成标志。(To achieve a single precision floating-point addition operations)
-
-
1下载:
《基于FPGA的单精度浮点数乘法器设计》详细介绍了按照IEEE754标准在FPGA上实现单精度浮点加减乘除的方法(The design of single precision floating point multiplier based on FPGA introduces in detail the way of realizing single precision floating point addition, subtraction and multiplication and div
-